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stm32 clock mux for CK48 definition #96353
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&pll { | ||
div-m = <4>; | ||
mul-n = <192>; | ||
div-p = <4>; | ||
div-q = <8>; | ||
clocks = <&clk_hse>; | ||
status = "okay"; | ||
}; | ||
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&rcc { | ||
clocks = <&pll>; | ||
clock-frequency = <DT_FREQ_M(96)>; | ||
ahb-prescaler = <1>; | ||
apb1-prescaler = <2>; | ||
apb2-prescaler = <1>; | ||
}; |
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Intentional change?
Would it be worth to add an alternate test with its own DTS overlay file?
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yes, when the sdmmc is clocked by the PLL_q, a freq = 48MHz is required.
This overlay file "f4_sdmmc48_pll.overlay"is for running this testcase by un-commenting.
The alternate test is "drivers.clock.stm32_clock_configuration.common_device.f4.sdmmc_48".
Two possible config are in this overlay (selection is by commenting/un-commenting). Is there any reason today to change with 2 different testcases/overlay files, if it was your question ?
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Ok, fine. Already having a test for SDMMC over CK48 seems enough.
I just found strange this added inline comments in this commit.
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LGTM.
Maybe the commit message could be more verbose on why the change, e.g.:
Define the STM32_CK48_ENABLED especially for the stm32F4 series
+when ck48 node is enabled to leverage its already implemented support.
&pll { | ||
div-m = <4>; | ||
mul-n = <192>; | ||
div-p = <4>; | ||
div-q = <8>; | ||
clocks = <&clk_hse>; | ||
status = "okay"; | ||
}; | ||
|
||
&rcc { | ||
clocks = <&pll>; | ||
clock-frequency = <DT_FREQ_M(96)>; | ||
ahb-prescaler = <1>; | ||
apb1-prescaler = <2>; | ||
apb2-prescaler = <1>; | ||
}; |
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Ok, fine. Already having a test for SDMMC over CK48 seems enough.
I just found strange this added inline comments in this commit.
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Nack until #94934 (comment) is fixed
efda26e
Add a commit to enable the clk48 |
comment updated |
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Comment below is not blocking.
@FRASTM, I think you need to rebase to get the CI tests to all succeed. |
Define the STM32_CK48_ENABLED especially for the stm32F4 series when ck48 node is enabled to leverage its already implemented support. Signed-off-by: Francois Ramu <[email protected]>
rebase on 9c5325d |
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@erwango, could you update your review status? You #96353 (review) comment was addressed: see #94934 (comment).
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This commit enables the clk48 clock mux if STM32_CK48_ENABLED is set by the device tree. Signed-off-by: Francois Ramu <[email protected]>
Define the STM32_CK48_ENABLED especially for the stm32F4 series
FIxes #94934